TECHNOLOGY PROFILE · TECH-0303
Tohoku-AISIN 16 nm STT-MRAM edge AI SoC
A university-industry 16 nm research system-on-chip integrating 32 MB of nonvolatile STT-MRAM with CPU, GPU and an AI accelerator, demonstrated with Tiny YOLOv3 object detection without external DRAM or SSD in the evaluated setup.
Tohoku University and AISIN joint first-party November 2, 2026 research announcements reviewed November 3; A-SSCC 2026 paper metadata identified, not independently replicated.. Added after the original November 1 snapshot; not a new product launch or independent benchmark replication.
Where it has an edge
Keeping the boot image and compact model weights in on-chip nonvolatile memory can reduce cold-start and external data-transfer costs for this particular small edge-vision workload; the authors report 65.7 ms OS boot and 124.2 ms power-on to first detection.
Best-fit problems
Studying low-startup-latency embedded vision architectures, near-memory computing and energy-versus-accuracy tradeoffs in controlled comparisons; not a purchasable deployment platform.
Tradeoffs & cautions
Publisher-reported evaluation-board numbers are not independently replicated or evidence of general superiority. The 65.7 ms figure measures OS boot, not first detection; first detection is 124.2 ms. The authors report 50.7 mJ per detection frame and mAP changing from 0.325 to 0.316 for Tiny YOLOv3. No commercial chip, public SDK, benchmark harness or software license was verified.
What to test before choosing
Request the conference paper, board, model, weights, compiler, power traces and exact comparison inputs. Reproduce cold boot, first-detection time, steady-state throughput, energy/frame, mAP and oversized-model behavior with matched OS and power settings.
Runtime & hardware
Authors describe a 16 nm FinFET SoC with 32 MB of embedded STT-MRAM, Arm Cortex-A53 CPU cores, Mali-G31 graphics and an AI accelerator. Demonstrated with Tiny YOLOv3; compatibility with arbitrary LLMs, models exceeding memory capacity or commercial toolchains is unknown.
Access & licensing
Research prototype only. Public ordering, SDK, RTL, design files, developer board, software licensing and independent reproduction materials were not established as available.
Execution
Research evaluation board only; deployment route unverified
Lifecycle
Controlled prototype presented at IEEE A-SSCC 2026, November 1-4; public product availability unverified
Comparison basis
First-party controlled Tiny YOLOv3 evaluation-board report using one comparator, not independent cross-vendor benchmarking; see the separate Atlas hardware-review.html evidence page for denominators and replication gaps.
Original notes
Added to Atlas on November 3; not a new commercial product. Reported external SSD/DRAM baseline: 2,535.3 ms OS boot plus 594.6 ms detection versus 65.7 ms plus 58.5 ms prototype. Ratios are workload-specific; full-text methods and DOI were not independently reviewed.
Connected concepts
Alternatives to investigate
Commercial edge inference SoCs or NPUs with developer kits · Microcontroller-class vision accelerators · Conventional CPU/GPU/accelerator systems with external DRAM and boot storage
Original source
Tohoku-AISIN 16 nm STT-MRAM edge AI SoC — original reference ↗